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Two Major Porints For Chip Designers: Flexibility And Shrinking Device Size

Auth:CGOCMALL Date:2018/11/8 Source:CGOCMALL Visit:265 Related Key Words: chip Semiconductor CGOCMALL
Looking at today's IoT and smart devices, you may feel that it is the best time to become a chip engineer. Devices are getting smaller and smaller, and more and more versatile integration into smaller sizes. From mobile phones to wearables to smart sensors for home, car and workplace, 2018 is a cutting-edge innovation year. Innovative and reflect the sense of the future.

But this innovative future is not so easy. You can ask any modern chip engineer. In fact, the pressure to develop cutting-edge innovative devices based on end-user expectations is exacerbating two special pain points that make engineers' jobs harder and harder.

What are the two points? The flexibility of the chip and the ever-shrinking device size.

The lack of flexibility of the chip will leave hidden dangers for the future.

In the field of electronic engineering, it is recognized that creating a large and expensive design has its corresponding advantages, that is, the design itself has great flexibility, programming ability and the ability to customize the chip according to individual needs. In turn, when engineers need to design smaller, cheaper electronics, they find that the flexibility and programmability at the design level drops to almost zero. The choice of components for this type of design is only: discrete devices with no options, no programming, and no flexibility.

This forces the engineers to carefully study the specific components they will use at the beginning of the design. Once they are fixed, they cannot be exchanged or changed. Otherwise, they may seriously disrupt their design work. In this way, it means that there is no degree of flexibility in the design process, which adds an unnecessary difficulty to the whole process. It requires engineers to demonstrate absolute perfect predictive power. Before the design work begins, they need to determine which discrete components are used, and these discrete components must be able to perform the functions of the design flawlessly. Choosing an error on any of the components can seriously overturn the entire project at some stage.

Or, engineers can really make no choice mistakes, but the needs of chip design can change in the middle of the design. If any of these two situations arise, engineers face sudden headaches, either correcting the error or adjusting to new chip requirements. This process can take days to weeks, or even months, and this can eventually lead to a chain reaction that delays the progress of all other processes waiting for the chip to be completed.

Smaller and smaller device sizes are tying the engineer's hands

Consumers continue to demand that portable devices become smaller and lighter. At the same time, consumers are demanding that these smaller and lighter devices can achieve longer battery life. For engineers, this means having to make more room in the device to place a larger battery for longer battery life.

These two requirements are opposite each other. For engineers, this is tantamount to a candle burning at both ends.

Even for applications such as smartphones, although the device does not become smaller in size, it may even be moving toward a larger form factor, but they also hope that the internal boards and components become smaller. In particular, reduce the electronic components in the device to free up more board space for more components, or replace existing components with a larger one, such as a larger battery.

Although the device may become smaller, there is generally at least one component on the board in the device that is still relatively large, such as a microcontroller or system-on-chip (SoC). This type is the core component, but it is also larger in size. Engineers have to include them in the design as usual, because manufacturers may say that the only thing they can get for this type of component is this one. Therefore, engineers can only design around the size of this SoC or microcontroller, and this will limit them...for example...improve battery cruising ability. If the board has been taken up by a lot of discrete devices, this problem is even more exacerbated, further tying the engineer's hands.

Smarter devices need to be equipped with smarter chip design engineering

As devices become smarter, more complex, and of course smaller, what components are used in these devices should not make the work of chip engineers unnecessarily difficult. Users want the devices to be intuitive to use. Why can't the engineers who design these devices become more intuitive?

Greater flexibility and a cleaner, crisper board space not only make life easier for engineers, but also benefit customers. A more flexible chip architecture means that customers and their engineers will have more room to decide which components are needed and when to decide which components are needed.

Chips with better board sizes enable better, smaller, and more efficient designs. Optimizing board space does not remove large components that must be retained, but can remove discrete components that are relatively unimportant but occupy valuable board space and replace them with more efficient components. If the optimized board space can be installed with larger and stronger batteries, is this a win-win for design companies and end users?

A good alternative to multiple small discrete devices is Dialog Semiconductor's GreenPAK configurable mixed-signal chip.

Good for engineers, but also for their customers, and ultimately will benefit users who use the product. If engineers have more room in the design, more flexibility, more options, more board space available, and will not disrupt design and production schedules due to later changes in demand, this will Benefit everyone. Smarter and more intuitive devices, with smarter and more intuitive chip design engineering.

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