Synopsys, Inc. announced that Synopsys' Design Platform fully supports TSMC WoW direct stacking and CoWoS advanced packaging technology. Design Platform supports the integration of 3D IC reference flows to help users deploy high-performance, highly-connected multi-die chips in applications such as mobile computing, network communications, consumer and automotive electronics.
Synopsys' Design Platform solutions include multi-die chip and interposer layout creation, physical layout planning and design implementation, parasitic extraction, timing analysis, and physical verification. The main products and features of Synopsys Design Platform supporting TSMC WoW and CoWoS advanced packaging technologies include:
IC Compiler II Place and Route: Supports multi-die chip layout planning and implementation, including interposer and 3D wafer stack generation, TSV layout and connection assignment, quadrature multilayer, 45 degree single layer, and die interconnect interface module Generated for parameter extraction and inspection between bare chip.
StarRC parameter extraction: support TSV and back RDL metal layer extraction, silicon interposer extraction, and coupling capacitor extraction between bare chips.
IC Validator: Supports full system DRC and LVS verification, bare chip interchip DRC and interface LVS verification.
PrimeTime signoff analysis: full system static timing analysis, support for multi-die chip static timing analysis (STA)
Suk Lee, senior director of TSMC Design Infrastructure Marketing, said: "High-performance advanced 3D silicon fabrication and wafer stacking technologies require new EDA features and processes to support higher design and verification complexity. We strengthen our approach with Synopsys The collaboration provides design solutions for TSMC's CoWoS and WoW advanced packaging technologies. We believe that design solutions will benefit both customers, improve designer productivity and speed time to market.
Michael Jackson, vice president of marketing and business development at Synopsys' Chip Design Division, said: "In-depth collaboration to support TSMC's WoW and CoWoS chip integration solutions design solutions and reference processes will enable our mutual customers to achieve optimal quality. As a result, Synopsys' Design Platform is able to meet the designer's schedule requirements and achieve a cost-effective, high-performance, low-power multi-die chip solution."
